Xgig EDSFF and OCP NIC 3.0 Analyzer Interposers for PCI Express 6.0

The VIAVI Xgig EDSFF Analyzer Interposers connect the VIAVI PCIe 6.0 Analyzer/Exerciser chassis to a system under test for capture at up to 64GT/s across 16 bi-directional lanes. The interposer installs into an EDSFF slot and provides a fully analog signal path between the root complex and the endpoint. It also passes a tap of the data traffic between the host and the endpoint device to the Analyzer/Exerciser chassis.

Variants are available for x16, x8 and x4 lane widths. Mechanical support covers E1.S, E1.L, E2, E3.S, E3.L and OCP NIC 3.0 modules through interchangeable front-end attachments and DUT carriers for each form factor. The front-end attachments can rotate 90 degrees so they can be positioned for each setup.

The interposer uses high-speed linear signal redrivers to buffer system data signals between the slot and the PCB fingers. This keeps the signal delivered to the Analyzer/Exerciser chassis and to the DUT clean enough for reliable protocol capture and analysis.

Test setup

The interposer is inserted into an E1, E2, E3 or OCP NIC 3.0 slot in the host system, and an EDSFF DUT carrier is installed into the interposer to create the test data path. Cables connect the interposer to the VIAVI Protocol Analyzer/Exerciser chassis, which captures tapped DUT data from both the upstream and downstream signal paths. The DUT system chassis must be open while the interposer is in use.

Together with the VIAVI PCIe 6.0 Analyzer/Exerciser chassis, the interposer supports debug and verification of new ICs, system hardware designs and FPGA firmware. It can also be used to validate system BIOS and software and for manufacturing test.