VIAVI Xgig Exerciser for PCI Express 5.0 PCIe Protocol Exerciser and Compliance Tester
PCIe 5.0 protocol exerciser that generates and responds to PCIe traffic at up to 32GT/s for compliance testing and debug.
- Maximum data rate
- 32GTps
- Supported data rates
- 2.5, 5.0, 8.0 and 16GTps
- Link widths
- 1, 2, 4, 8 and 16-lanes
- Speed transitions
- any speed/width to any other
Overview
The VIAVI Xgig Exerciser for PCI Express 5.0 adds turn-key protocol compliance test capability to the Xgig PCIe product portfolio. It generates PCIe data streams and responds to PCIe inputs with appropriate branching, giving full, bit-level, repeatable control over PCIe traffic for debugging difficult protocol communication problems.
The Exerciser operates in two modes: Root Complex (RC) or host mode, which enables endpoint testing, and End Point (EP) mode, which enables testing of a host system. It supports detailed validation and debug of a PCIe controller's state machine as well as debug and performance tuning of firmware and application software. It can also be programmed with non-compliant PCIe sequences to test boundary and stress conditions that are otherwise difficult to evaluate.
Analyzer integration and scripting
The Exerciser works in tight association with the Xgig Analyzer function to provide detailed bit-level trace capture. Bidirectional data of hundreds of gigabytes can be saved for analysis with VIAVI tools such as Expert. A scripting API allows complex, custom test scripts to be created, either from scratch or modified from pre-defined library scripts. Interposers provide the physical link between the Xgig 5P16 PCIe 5.0 platform chassis and the device under test, with different interposers for endpoint devices or host systems.
Compliance testing
PCI-SIG certification covers electrical and protocol testing; protocol testing is performed with PCIe exercisers. The Xgig Exerciser enables pre-certification to the Protocol Compliance test suite. Tests can be run individually, in groups or in sequence, with a pass-fail result and an optional full trace of the communication. Pre-defined compliance tests are locked to follow PCI specifications but can be copied, edited and saved as new scripts.
User interface
The graphical user interface runs on a Windows 10 PC and provides Settings (test bench configuration, clocking, reset, LTSSM link controls, TX/RX settings, timeouts, data rate and link width limits), a Compliance Test panel for selecting tests, and a Config Space panel for defining the Exerciser's PCIe configuration space parameters, with current test and bench status always shown.
Key Features
- Emulates either a Root Complex or an End Point device
- Generates and responds to PCIe compliant data packets
- Operates to 32GT/s and supports PCIe data rates of 2.5, 5.0, 8.0 and 16GT/s
- Supports link widths of 1, 2, 4, 8 and 16 lanes
- Set link rates and widths and control transitions to other rates
- Tightly aligned operation with the Analyzer for bit-level trace captures
- Executes the PCIe compliance test suite
- LTSSM testing with both positive and negative test scenarios
- LTSSM state tracker with history log
- Define, save and load custom test configurations
- Define custom test suites and execution sequence
- Swap DLLP ACK to NAK responses and modify CRC
- Define, send and modify Ordered Sets
- Template libraries available
- Scripting API for complex test cases
- Graphical control interface for visual setup of test procedures
- Xgig tools and Exerciser user interface run on a Windows 10 PC
- Runs on the VIAVI 5P16 Analysis Platform chassis, Xgig5P-PCIe5-X16-PF
- Works with the Xgig5P-PCIe5-X16-EH Exerciser Host-Mode Test Stand
- Interposers available for endpoint or host system testing
Specifications
| Maximum data rate | 32GTps |
|---|---|
| Supported data rates |
2.5, 5.0, 8.0 and 16GTps
In addition to 32GTps
|
| Link widths |
1, 2, 4, 8 and 16-lanes
Maximum width depends on license key
|
| Speed transitions | any speed/width to any other |
| Operating modes |
Root Complex (RC) or host mode and End Point (EP) Mode
RC mode enables endpoint testing; EP mode enables host system testing
|
|---|
| Supported states | Detect, Quiet, Configuration, L0, L1, Recovery |
|---|
| TLP packet types |
TLP 32b memory, TLP 64b memory, TLP IO, TLP configuration, TLP message packets
Bad TLP packets can also be executed
|
|---|---|
| Config space headers | Config Space Type 0 Headers (32b), Config Space Type 1 Headers (64b) |
| Error injection |
Inject disparity errors, symbol errors, Sync Bit errors
Option
|
| Platform | VIAVI 5P16 Analysis Platform chassis, Xgig5P-PCIe5-X16-PF |
|---|---|
| Host PC |
Windows 10 enabled PC
For Xgig tools and the Exerciser user interface
|
| License lane configurations | up-to 16-lanes, 8-lanes or 4-lanes |
Specifications are taken from the manufacturer's documentation. See the datasheet for complete and current values.
Applications
- PCIe 5.0 protocol compliance pre-certification
- PCIe endpoint device testing
- PCIe host system testing
- PCIe controller state machine validation and debug
- Firmware and application software debug and performance tuning
- Boundary and stress condition testing
- LTSSM link training testing
- Error injection testing
Options & Accessories
| Option | Description |
|---|---|
| Xgig5P-PCIe5-X16-EX | Xgig 16-lane Exerciser License Key for PCIe 5.0 |
| Xgig5P-PCIe5-X8-EX | Xgig 8-lane Exerciser License Key for PCIe 5.0 |
| Xgig5P-PCIe5-X4-EX | Xgig 4-lane Exerciser License Key for PCIe 5.0 |
