Xgig E3 EDSFF 16-Lane Interposer Module Xgig5P-PCIe5-X16-E3 for PCI Express 5.0

16-lane EDSFF E3 interposer that taps PCIe 5.0 traffic at up to 32 GT/s between a storage server and an E3.S or E3.L NVMe SSD for protocol analysis.

Maximum data rate: 32GT/s, PCIe 5.0
Downward compatible data rates: 2.5, 5.0, 8.0G and 16GT/s
Link configurations: 1 link of 16 lanes or 1 link of 4 or 8 lanes
Capture: Bidirectional PCIe 5.0 protocol data on up to 16 lanes at 32 GT/s

Datasheet

Overview

The VIAVI Xgig5P-PCIe5-X16-E3 is an interposer for PCI Express 5.0 that is built for developing, debugging and tuning the performance of NVMe SSDs in high-density storage servers. It taps the data signals between the host system and an EDSFF NVMe SSD and passes them to a VIAVI analyzer. Bidirectional PCIe 5.0 protocol data on up to 16 lanes can be captured at 32 GT/s.

The interposer ships with two user-swappable front-end modules, E3.L (long) and E3.S (short), so it fits the target system. The E3.S module fits the 7.5 mm Short Form Factor with Optional Symmetric Enclosure variation. The interposer supports one link of 4 or 8 lanes, or one link of 16 lanes.

High-speed linear signal redrivers buffer the system data signals as they cross the interposer between the host system and the SSD under test. This gives the analyzer a clean signal for protocol capture and analysis.

Setup and operating modes

To set up the interposer, an E3 EDSFF SSD is inserted into the interposer base pod. The front-end module then goes into the EDSFF bay of the storage server, and cables connect the interposer to the VIAVI PCIe 5.0 Analyzer/Exerciser/Jammer platform. The Xgig analysis tools run on a local or remote Windows PC. In Analyzer mode, the interposer taps DUT data from both the upstream and downstream paths. In Analyzer/Jammer mode, data passes through the analyzer and is modified between the DUT devices. In Analyzer/Exerciser mode, the analyzer chassis sources the data and sends it to the server device under test through the interposer.

Key Features

Operates up to 32GT/s, PCIe 5.0 data rates
Downward compatible with PCIe data rates of 2.5, 5.0, 8.0 and 16GT/s
Supports 1 link of 4 or 8 lanes or 1 link of 16 lanes
EDSFF E3.S or E3.L NVMe SSD DUT (not supplied) plugs directly into the interposer
Supplied with user-swappable E3.L and E3.S front-end modules
Includes high-quality custom cables for analyzer connection
Data path uses high-speed linear redrivers for good signal capture with little or no tuning
Supports analyzer side-band signal capture and triggering with display in multiple formats
Supplied power brick makes interposer power independent of the host system
LEDs give quick indicators of power and status
Consistent, repeatable capture of link training, equalization negotiation and other data
Supports error injection (jamming) for deep system analysis
Works with the VIAVI Xgig 5P8 and 5P16 PCIe 5.0 Analyzer/Exerciser/Jammer chassis
Supported by the Xgig tool suite including Trace Control, Expert and Serialytics

Specifications

Protocol

Maximum data rate	32GT/s, PCIe 5.0
Downward compatible data rates	2.5, 5.0, 8.0G and 16GT/s
Link configurations	1 link of 16 lanes or 1 link of 4 or 8 lanes
Capture	Bidirectional PCIe 5.0 protocol data on up to 16 lanes at 32 GT/s

Device Under Test

Supported DUT	EDSFF E3.L or E3.S NVMe SSD DUT not supplied
E3.S form factor fit	7.5 mm Short Form Factor with Optional Symmetric Enclosure variation

Physical

Base Pod size	160 x160 x 35 mm
E3.L front-end module size	158 x 7.5 x 76 mm L x T x H
E3.S front-end module size	128 x 7.5 x 76 mm L x T x H

Power

Power brick	120/220 input, 12V/3A output

Specifications are taken from the manufacturer's documentation. See the datasheet for complete and current values.

Applications

NVMe SSD development, debugging and performance tuning in high-density storage servers
Verification of new PCIe or CXL controller ICs
New server design verification
Firmware tuning
Manufacturing test verification
Validation of system BIOS and software
NVMe SSD and CXL EDSFF debugging